The present invention relates to a semiconductor integrated circuit device and a technique for manufacturing the same and, more particularly, to a technique which is effective if applied to a semiconductor integrated circuit device having a SRAM (i.e., Static Random Access Memory).
The SRAM, as acting as a semiconductor memory device, is equipped with memory cells a memory cell which is disposed at an intersection between a word line and a pair of complementary data lines and composed of a flip-flop circuit and two transfer MISFETs (i.e., Metal Insulator Semiconductor Field Effect Transistors).
The flip-flop circuit of the memory cell of the SRAM is constructed as an information storage unit for storing information of 1 bit. This flip-flop circuit of the memory cell is exemplified by a pair of CMOS (i.e., Complementary, Metal Oxide Semiconductor) inverters. Each of the CMOS inverters is composed of n-channel type drive MISFETs and p-channel load MISFETs. On the other hand, transfer MISFETs are of the n-channel type. In short, this memory cell is of the so-called xe2x80x9cCMOS (i.e., Full Complementary Metal Oxide Semiconductor)xe2x80x9d using the six MISFETs. Incidentally, the complete CMOS type SRAM, which is formed over the principal surface of the semiconductor substrate with the drive MISFETs, the load MISFETs and the transfer MISFETs, will be called the xe2x80x9cbulk CMOS type SRAMxe2x80x9d. This bulk CMOS type SRAM is disclosed, for example, on pp. 590 to 593 of IEDM (i.e., International Electron Device Meeting), Technical Digest, 1985.
In the SRAM of this kind, the paired CMOS inverters constituting the flip-flop circuit have their input/output terminals crossly connected with each other through a pair of wiring lines (as will be called the xe2x80x9clocal wiring linesxe2x80x9d). One of the CMOS inverters has its input/output terminals connected with the source region of one of the transfer MISFETs, and the other CMOS inverter has its input/output terminals connected with the source region of the other transfer MISFET. One of the complementary data lines is connected with the drain region of one of transfer MISFETs, and the other complementary data line is connected with the drain region of the other transfer MISFET. With the individual gate electrodes of the paired transfer MISFETS, there is connected word lines, by which are controlled the ON/OFF of the transfer MISFETs. In the above-specified Publication, the local wiring lines are formed by a self-aligning silicide process. This silicide process per se is disclosed on pp. 118 to 121 of IEDM, Technical Digest, 1984.
As the capacity of a semiconductor memory device grows larger and larger according to the progress of the miniaturizing technique in recent years, the area to be occupied by the memory cell of the aforementioned bulk CMOS type SRAM grows smaller and smaller. However, when the area occupied by the memory cell is reduced, the storage node capacity (i.e., the pn junction capacity or gate capacity parasitic to the aforementioned storage nodes A and B) of the memory cell is reduced to reduced the amount of stored charge.
As a result, the resistance to the information inversion (i.e., the so-called xe2x80x9cxcex1 ray soft errorxe2x80x9d) of the memory cell due to the xcex1 ray having irradiated the surface of the semiconductor chip is lowered to make it difficult to retain the safe operation of the memory cell. In order to promote the miniature structure without deteriorating the stable operation of the memory cell, therefore, the counter-measures for retaining the amount of stored charge are indispensable.
More specifically, if the memory cell is irradiated with the xcex1 ray which is emitted when a radioactive element, as contained in a trace amount in a package or resin material used for sealing the memory cell, such as uranium or thorium disintegrates, electron/hole pairs are produced along the range of the a ray to immigrate into the pn junction forming the storage node so that the information of the memory cell is broken. This phenomenon is called the xe2x80x9csoft errorxe2x80x9d. In the bulk CMOS type SRAM of the prior art, because of the large memory cell area, the capacity of the storage node itself, as composed of a pn junction capacity or a gate capacity, and the driving ability of the load MISFETs is so high that the storage node can be stored with charge sufficient for compensating the charge loss due to the xcex1 ray. If the memory cell area is miniaturized, however, the amount of charge to be stored in the storage node is also reduced to raise a problem that the resistance of the memory cell to the irradiation of the xcex1 ray is deteriorated.
Specifically, we have found that new counter measures for retaining the charge storing amount of the memory cell is indispensable in the bulk CMOS type SRAM, too, for further miniaturizing the memory cell of the SRAM.
An object of the present invention is to provide a technique capable of improving the resistance to the soft error by increasing the storage node capacity of the memory cell of the SRAM.
Another object of the present invention is to provide a technique capable of miniaturizing the memory cell of the SRAM.
Another object of the present invention is to provide a technique capable of operating the memory cell of the SRAM at a high speed and at a low voltage.
Another object of the present invention is to provide a technique capable of improving the production yield and reliability of the memory cell of the SRAM.
The foregoing and other objects and novel features of the present invention will become apparent from the following description to be made with reference to the accompanying drawings.
The representative ones of the invention to be disclosed herein will be summarized in the following.
(1) A semiconductor integrated circuit device including a SRAM having a memory cell comprising: a flip-flop circuit composed of a pair of CMIS inverters having drive MISFETs and load MISFETs; and a pair of transfer MISFETs connected with a pair of input/output terminals of said flip-flop circuit, wherein a first conducting layer is formed over the principal surface of a semiconductor substrate to form the individual gate electrodes of said drive MISFETS, said load MISFETs and said transfer MISFETs, wherein a second conducting layer is formed over said first conducting layer to form a pair of local wiring lines for connecting the individual input/output terminals of said paired CMIS inverters, wherein a third conducting layer is formed over said second conducting layer to form a reference voltage line to be connected with the source region of said drive MISFETS, and wherein said reference voltage line is arranged to be superposed over said paired local wiring lines.
(2) In the aforementioned SRAM, a semiconductor integrated circuit device, wherein said local wiring lines are partially extended over the gate electrode of said drive MISFETs, said load MISFETs or said transfer MISFETS.
(3) In the aforementioned SRAM, a semiconductor integrated circuit device, wherein said local wiring lines are partially extended over a semiconductor region constituting the input/output terminals of said CMIS inverters.
(4) In the aforementioned SRAM, a semiconductor integrated circuit device, wherein there is formed over said reference voltage line a fourth conducting layer which is made of a conducting material having a lower resistance than that of said third conducting layer constituting said reference voltage line, for supplying a reference voltage, and wherein said fourth conducting layer and said reference voltage line are electrically connected through at least one connection hole which is formed in each memory cell.
(5) In the aforementioned SRAM, a semiconductor integrated circuit device, wherein the connection hole for connecting said fourth conducting layer and said reference voltage line and the connection hole for connecting the reference voltage line and the source region of said drive MISFETs are spaced from each other.
(6) In the aforementioned SRAM, a semiconductor integrated circuit device, wherein said local wiring lines are made of a refractory metal silicide film.
(7) In the aforementioned SRAM, a semiconductor integrated circuit device, wherein the refractory metal silicide layer of said second conducting layer is formed over the drain region of said transfer MISFETs, wherein a pad layer of said third conducting layer is formed over said refractory metal silicide layer, and wherein a data line is connected with said drain region through said pad layer and said refractory metal silicide layer.
(8) In the aforementioned SRAM, a semiconductor integrated circuit device, wherein the refractory metal silicide layer of said second conducting layer is formed over the source region of said load MISFETs, wherein a pad layer of said third conducting layer is formed over said refractory metal silicide layer, and wherein a reference voltage is supplied to said drain region through said pad layer and said refractory metal silicide layer.
(9) In the aforementioned SRAM, a semiconductor integrated circuit device, wherein a well energizing semiconductor region having a conduction type different from that of said source region is formed over the principal surface of the semiconductor substrate adjacent to the source region of said load MISFETs.
(10) In the aforementioned SRAM, a semiconductor integrated circuit device, wherein the gate electrode of said transfer MISFETs is made of a conducting layer lying over said first conducting layer in place of means made of said first conducting layer.
(11) In a SRAM having a memory cell comprising: a flip-flop circuit composed of a pair of CMOS inverters having drive MISFETs and load MISFETs; and a pair of transfer MISFETs connected with a pair of input/output terminals of said flip-flop circuit, a semiconductor integrated circuit device wherein a first conducting layer is formed over the principal surface of a semiconductor substrate to form the individual gate electrodes of said drive MISFETs, said load MISFETs and said transfer MISFETs, wherein a second conducting layer is formed over said first conducting layer to form a pair of local wiring lines for connecting the individual input/output terminals of said paired CMOS inverters, wherein a third conducting layer is formed over said second conducting layer to form a supply voltage line to be connected with the source region of said load MISFETs, and wherein said supply voltage line is arranged to be superposed over said paired local wiring lines.
(12) A process for manufacturing a semiconductor integrated circuit device having wiring lines for connecting a first semiconductor region of a first conduction type and a second semiconductor region of a second conduction type, which are formed over a semiconductor substrate at a spacing from each other, comprising the following steps (a) to (d):
(a) the step of selectively forming a first silicon layer on the individual surfaces of said first semiconductor region and said second semiconductor region;
(b) the step of forming a refractory metal film all over the surface of the semiconductor substrate, as covers said first silicon layer;
(c) the step of patterning a second silicon layer into the shape of said wiring lines after said second silicon layer is formed over said refractory metal film; and
(d) the step of thermally treating said semiconductor substrate to silicify said first silicon layer, said refractory metal film and said second silicon layer, and then removing said refractory metal film left unreacted over said semiconductor substrate.
(13) In a process for manufacturing a SRAM having a memory cell comprising: a flip-flop circuit composed of a pair of CMIS inverters having drive MISFETs and load MISFETs; and a pair of transfer MISFETs connected with a pair of input/output terminals of said flip-flop circuit, a process for manufacturing a semiconductor integrated circuit device, wherein a pair of local wiring lines for connecting the input/output terminals of said paired CMIS inverters with each other are formed by the following steps (a) to (d):
(a) the step of selectively forming a first silicon layer on the individual surfaces of a first semiconductor region of a first conduction type and a second semiconductor region of a second conduction type, which constitute the input/output terminals of said CMIS inverters, and on the partial surfaces of the individual gate electrodes of said drive MISFETs and said load MISFETs;
(b) the step of forming a refractory metal film all over the surface of a semiconductor substrate, as covers said first silicon layer;
(c) the step of patterning a second silicon layer into the shape of local wiring lines after said second silicon layer is formed over said refractory metal film; and
(d) the step of thermally treating said semiconductor substrate to silicify said first silicon layer, said refractory metal film and said second silicon layer and then removing said refractory metal film left unreacted over said semiconductor substrate.
(14) In a process for manufacturing said SRAM, a semiconductor integrated circuit device manufacturing process, further comprising, before said step (a): the step of removing the thick insulating film covering the portions of the individual gate electrodes of said drive MISFETs and said load MISFETs, by the dry etching method using a photoresist as the mask; and the step of removing the thin insulating film, which covers the individual surfaces of said first semiconductor region and said semiconductor region, by etching back the entire surface of said semiconductor substrate, while leaving said thin insulating film on the side walls of said gate electrode.
(15) In a process for manufacturing said SRAM, a semiconductor integrated circuit device manufacturing process, wherein the refractory metal silicide layer formed on the individual surfaces of said first semiconductor region and said second semiconductor region has a higher bottom face than the top face of the gate insulating film of said drive MISFETs and said load MISFETs.
(16) In a process for manufacturing said SRAM, a semiconductor integrated circuit device manufacturing process, wherein when said second silicon layer is not left, when patterned at said step (c) into the shape of said local wiring lines, on at least a portion of such one of the individual semiconductor regions of said drive MISFETs and said load MISFETs as does not constitute the input/output terminals of said CMIS inverters.
(17) In a process for manufacturing said SRAM, a semiconductor integrated circuit device manufacturing process, wherein a reference voltage line or a supply voltage line is formed over said local wiring lines after said step (d), and wherein a capacity is formed between said local wiring lines and said reference voltage line or said supply voltage line.
(18) In a process for manufacturing said SRAM, a semiconductor integrated circuit device manufacturing process, wherein the second silicon layer, as formed over said refractory metal film at said step (c), is made thicker than the thickness necessary for said silification.
(19) In a process for manufacturing said SRAM, a semiconductor integrated circuit device manufacturing process, wherein a second refractory metal film or its silicide film is formed over said second silicon layer after said second silicon layer is formed over said refractory metal film at said step (c).
(20) In a process for manufacturing said SRAM, a semiconductor integrated circuit device manufacturing process, wherein a refractory metal silicide film is formed simultaneously with said local wiring line forming step on such one of the individual semiconductor regions of said drive MISFETs, said transfer MISFETs and said load MISFETs as is connected with any of said data line, said supply voltage line and said reference voltage line.
According to the aforementioned means (1), (11) and (17), the reference voltage line to be formed over the local wiring lines is arranged to be superposed over the local wiring lines so that the capacity element is formed between the reference voltage line and the local wiring lines. As a result, the capacity of the storage nodes, as connected with the local wiring lines, can be increased to improve the resistance of the memory cell to the xcex1 ray soft error.
According to the aforementioned means (2), the local wiring lines are arranged to be partially superposed over the gate electrodes of the drive MISFETs, the load MISFETs or the transfer MISFETs so that the gate capacity component of the storage node capacity can be increased. As a result, the storage node capacity of the memory cell can be increased to improve the resistance to the a ray soft error.
According to the aforementioned means (3), the local wiring lines are arranged to be partially superposed over the storage nodes of the memory cell so that the capacity component of the diffusion layer of the storage node capacity can be increased. As a result, the storage node capacity of the memory cell can be increased to improve the resistance to the a ray soft error.
According to the aforementioned means (4), over the reference voltage line, there is arranged the wiring line having a lower resistance, and the electric power is supplied from the lower-resistance wiring line to the reference voltage through the connection holes which are formed in at lest one in each memory cell. As a result, the electric power of the reference voltage line can be supplied to each memory cell so that the reference voltage can be stabilized. As a result, the minimum value (Vcc.min) of the supply voltage can be improved to improve the resistance of the memory cell to the a ray soft error.
According to the aforementioned means (5), the connection holes for connecting the lower-resistance wiring line and the reference voltage line and the connection holes for connecting the reference voltage line and the source region of the drive MISFETs are spaced from each other so that the step, which might otherwise be formed by the overlap of those connection holes, can be avoided to flatten the connection hole forming regions. As a result, the connection holes can have their contact resistances reduced to operate the memory cell at a high speed and at a low voltage.
According to the aforementioned means (12) and (13), the local wiring lines are formed by causing the silicifying reaction among the polycrystalline silicon film, the refractory metal film deposited on the former, and the second polycrystalline silicon film deposited on the former, so that the silicon in the semiconductor regions forming the storage nodes of the memory cell can be prevented from participating in the aforementioned silicifying reaction. As a result, the junction leakage current of the semiconductor regions can be reduced to improve the operational reliability of the memory cell.
According to the aforementioned means (14), the step of forming the connection holes in the portions of the gate electrodes and the step of exposing the semiconductor regions are carried out separately of each other to make the allowance unnecessary for the mask alignment between the connection holes and the semiconductor regions, so that the areas for the connection holes can be reduced to highly integrate the memory cell. By connecting the local wiring lines and the semiconductor regions in self-alignment, moreover., no allowance is required for the mask alignment of the two so that the memory cell size can be reduced to highly integrate the memory cell.
According to the aforementioned means (6), (12) and (13), the paired local wiring lines for connecting the storage nodes of the memory cell are made of the refractory metal silicide, so that the p-type impurity in the semiconductor region of the load MISFETs and the n-type impurity in the semiconductor region or the gate electrodes of the drive MISFETs can be prevented from diffusing into each other through the local wiring lines. As a result, the ohmic connections can be made with a low resistance between the semiconductor regions of the different conduction types and between the semiconductor region and the gate electrodes thereby to operate the memory cell at a high speed and at a low voltage.
According to the aforementioned means (15), even in the case of a misalignment of the photoresist to be used as the mask at the time of etching the overlying polycrystalline silicon film, it is possible to prevent the underlying polycrystalline silicon film from being scraped. As a result, the allowance for the alignment of the photoresist can be eliminated to reduce the areas for the semiconductor regions thereby to highly integrate the memory cell.
According to the aforementioned means (7), (8) and (20), the refractory metal silicide layers are formed on the surfaces of at least the portions of the individual source regions and drain regions of the transfer MISFETs, the drive MISFETs and the load MISFETs, as constituting the memory cell, so that the source regions and the drain regions can have their resistances lowered. As a result, it is possible to operate the memory cell at a high speed and at a low voltage.
According to the aforementioned means (9), the source region, the well energizing drain region and the supply voltage line can be ohmically connected without considering the conduction type of the polycrystalline silicon pad layer, as formed on the refractory metal silicide layer, so that the source region and the well energizing drain region of the load MISFETs can be simultaneously supplied with the supply voltage through the one connection hole. As a result, the source region and the well energizing drain region of the load MISFETs can be arranged adjacent to each other and can have their areas reduced to highly integrate the memory cell.
According to the aforementioned means (18), when the local wiring lines are to be formed by the silicifying reaction, their thickness and surface areas are increased by making the polycrystalline silicon film, as deposited on the refractory metal silicide layer, thicker than that necessary for that silicifying reaction, so that the capacity to be established between the local wiring lines and the overlying reference voltage line is increased. As a result, the storage node capacity of the memory cell can be further increased to improve the resistance to the xcex1 ray soft error.